Design and Implementation of Cmos Pwm Transceiver by Using Self Referenced Edge Detection Technique

A CMOS PWM Transceiver is designed and implemented with the help of self referenced Edge Detection technique. The Transceiver is designed with out the use of Phase locked loop which occupies large area and large amount of Power supply. Edge detection technique contrast the difference between the rising edge and modulated falling edge. The modulated falling edge is delayed by 0.5T in one carrier clock cycle. It accomplished area efficient, high robustness by PWM. The measured results by 0.12μm CMOS technology describe 2-bit communication, with small area 0.003536μm 2 , power dissipation is 1.02mw and requirement of power supply is 1.20v. For improving the reliability, error check and correction circuit is implemented and evaluated by 1bit PWM